The present invention relates to a semiconductor device, and more particularly, to a data reception device for receiving packet data based on the IEEE 1394 standard.
FIG. 1 is a schematic block diagram of a conventional reception port RP incorporated in a device for transmitting and receiving packet data in compliance with the IEEE 1394 standard. A decoder 1 receives reception data Din and a reception clock signal clk1, decodes the coded reception data Din in accordance with the reception clock signal clk1, and descrambles the reception data Din.
A synchronization-shaping first-in first-out (FIFO) memory 2 receives the decoded reception data Dde. The synchronization-shaping FIFO memory 2 performs a synchronization process and a data shaping process on the reception data Dde. More specifically, the synchronization-shaping FIFO memory 2 synchronizes the reception data Dde with an internal clock signal clk2 and data-shapes the reception data Dde so that it is output to an internal circuit in fixed cycles.
FIG. 2 is a timing chart showing the synchronization operation of the decoder 1 and the synchronization-shaping FIFO memory 2. The decoder 1 sequentially decodes the reception data Din in packet units data1 to datan in accordance with the reception clock signal clk1 and provides the decoded reception data Dde to the synchronization-shaping FIFO memory 2. The decoding process requires time t1 corresponding to, for example, three cycles of the reception clock signal clk1.
Next, the synchronization-shaping FIFO memory 2 synchronizes the reception data Dde with the internal clock signal clk2 and provides the synchronized reception data Dsc to the internal circuit. The synchronization process requires time t2 corresponding to two cycles of the internal clock signal clk2. The reception clock signal clk1 is set at 12.288 MHz, 24.576 MHz, or 49.152 MHz depending on the device. The internal clock signal clk2 is set at, for example, 100 MHz.
FIG. 3 shows a data string of each packet of the reception data Dde that is provided to the synchronization-shaping FIFO memory 2. The reception data Dde is transmitted in packets. Each packet of the reception data Dde sequentially includes an idle signal, a request signal, DATA PREFIX, packet data, and DATA END. After the transmission of one packet, the idle signal of the next packet is provided to the synchronization-shaping FIFO memory 2.
The segments of DATA PREFIX, the packet data, and the DATA END each have a standardized data length (byte length). During data transfer, dropout errors of the data segments having the standardized data lengths are not allowed. The data lengths of the idle signal and the request signal do not have to be determined.
In the synchronization-shaping FIFO memory 2, the reception data Dde is synchronized with the internal clock signal clk2 and sequentially stored in the shaping FIFO memory. The synchronized reception data Dsc stored in the shaping FIFO memory is shaped so that the shaped reception data Dsu is provided sequentially in fixed bytes to the internal circuit at predetermined cycles.
Japanese Laid-Open Patent Publication No. 1-500950 describes a reception device that enables clock synchronization without any dropout errors of input data bits. The reception device includes a FIFO memory, for storing an input data signal, and a synchronization unit, for controlling the delay of an output from the FIFO memory until the data signal is synchronized with a clock signal.